It's 2025, chip design doesn't have to be difficult! Transform your workflow with
automated SoC design.
How does SoC Gen work?
SoC Specifications
Simple editable SoC specs serve as a central source of info for the entire flow.
Automation
Automation to reduce redundancy, minimize human error, and ensure consistency in SoC development
RTL
Verification
Software
Documentation
The outputs address 4 key areas of SoC development: Hardware, Verification, Software & Documentation
SoC Gen Output
SoC Subsystem RTL
Connectivity
RISC-V Cores
AXLs
UnCore
NoC
Peripheral IPs
IP Collateral Generated
Software
GCC GNU Toolchain
LLVM Toolchain
GBD
OpenOCD
ISA Models
SW Dev Kit (SDK)
Integrated Dev Env
Standard OS BSPs
Verification
eUVM based Flow
GCC GNU Toolchain
GCC GNU Toolchain
LLVM Toolchain
GBD
OpenOCD
ISA Models
SW Dev Kit (SDK)
Integrated Dev Env
Standard OS BSPs
Ready2Use Ref-SoC
Ready2Use Ref-SoC
Xilink Board IP
Extendable SoCs
ASIC
Constraints
Lint Scripts
Synth Scripts
One tool, many benefits
Hardware Design Team
Documentation Team
Verification Team
SoC Gen
System Architecture Team
System Architecture Team
FPGA Prototyping Team
Project Management Team
Business Impact
Reduce $$, time, risk of new SoC design starts
Seamless Transition to a RISC-V SoC
Streamline IP Management
A wingman for Frontend Engineers
case study
A secure SoC subsystem built by SoC Gen in minutes.
Features
- AES accelerator with support for various modes
- SHA accelerator (256/512) with performance or area optimised variants
- Big number accelerator for RSA and ECC algorithms
- Secret Keystore: secret keys cannot be leaked by any agent including the processor
- Secure Memory module to store user data in a secure manner
- Worldguard based trusted execution environment
- Secure Boot framework: elf signing, key management and boot code using security accelerators
- Standard RISC-V security features: privilege modes (M,S,U,HS,VS,VU) and PMPs
- Secure debug module
- On-the-fly memory encryption of all code and data between processor and memory
Bring your own IP
How we do it
- Automated wrapper construction for your IP (the largest IP wrapper takes 3-4 days + 1 day for RTL collateral integration).
- Python plugin for the IP to work with the generator.
Ready to build Smarter, Faster and Scalable SoCs?
Join the innovators transforming the future of chips design. Let InCore’s SoC Generator take you from concept to silicon seamlessly.
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