RISC-V: Unveiling the Potential of Open-Source ISA
RISC-V, an open ISA based on RISC principles, originated at UC Berkeley around 2010 and was standardized in 2013. It gained traction as an alternative to proprietary ISAs like ARM or x86 due to its open-source nature and customizable features. Its configurability and modularity have fueled its rapid adoption, allowing vendors to tailor processors for various workloads. InCore leverages this modularity to design highly configurable processors, offering tailored instances for specific RISC-V subsets. With its open-source, scalable architecture, RISC-V provides significant advantages for developers, making it an exciting technology for the future.
Core-hub Generators: Streamlining Custom Processor Design
What makes us different : Automated design flow
SaaS agility to hardware
CI/CD brings SaaS-like agility to hardware, enabling rapid prototyping, automated testing, and seamless iteration—accelerating development, reducing time-to-market, and ensuring scalable, high-quality products.
Automated verification
Automated generators ensure thorough testing, corner case coverage, and ISA/uARCH compliance, while continuous integration and regression testing maintain high verification standards.
Parametrized Libraries
BSV’s parametrized libraries enable correctness by construction, enhancing efficiency, reliability, and quality while reducing bugs and design cycle time for complex SoC designs.
YAML to all things silicon
Pre-defined templates
We simplify custom hardware development with pre-defined SoC templates that are aligned with market trends and requirements.
FPGA flows
We streamline FPGA prototyping on platforms like Xilinx, enabling instant setup for firmware and software teams, enhancing collaboration and productivity for success.
ASIC flows
We accelerate ASIC flows, allowing PPA targets to be met rapidly leading to significant reduction in design cycles.
Doc Generator: Streamlining Documentation for Core Instances
Our Doc Generator uses the same YAML spec used to generate our Core-hubs. This ensures that the documentation is never out of sync with the code.
Core-hub Generators: Streamlining Custom Processor Design
What makes us different : Automated design flow
SaaS agility to hardware
CI/CD brings SaaS-like agility to hardware, enabling rapid prototyping, automated testing, and seamless iteration—accelerating development, reducing time-to-market, and ensuring scalable, high-quality products.
Automated verification
Automated generators ensure thorough testing, corner case coverage, and ISA/uARCH compliance, while continuous integration and regression testing maintain high verification standards.
Parametrized Libraries
BSV’s parametrized libraries enable correctness by construction, enhancing efficiency, reliability, and quality while reducing bugs and design cycle time for complex SoC designs.
YAML to all things silicon
Pre-defined templates
We simplify custom hardware development with pre-defined SoC templates that are aligned with market trends and requirements.
FPGA flows
We streamline FPGA prototyping on platforms like Xilinx, enabling instant setup for firmware and software teams, enhancing collaboration and productivity for success.
ASIC flows
We accelerate ASIC flows, allowing PPA targets to be met rapidly leading to significant reduction in design cycles.
Doc Generator: Streamlining Documentation for Core Instances
Our Doc Generator uses the same YAML spec used to generate our Core-hubs. This ensures that the documentation is never out of sync with the code.
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